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? semiconductor components industries, llc, 2006 april, 2006 ? rev. 3 1 publication order number: ne5517/d ne5517, ne5517a, AU5517 dual operational transconductance amplifier the AU5517 and ne5517 contain two current-controlled transconductance amplifiers, each with a differential input and push-pull output. the AU5517/ne5517 offers significant design and performance advantages over similar devices for all types of programmable gain applications. circuit performance is enhanced through the use of linearizing diodes at the inputs which enable a 10 db signal-to-noise improvement referenced to 0.5% thd. the AU5517/ne5517 is suited for a wide variety of industrial and consumer applications. constant impedance of the buffers on the chip allow general use of the AU5517/ne5517. these buffers are made of darlington transistors and a biasing network that virtually eliminate the change of offset voltage due to a burst in the bias current i abc , hence eliminating the audible noise that could otherwise be heard in high quality audio applications. features ? constant impedance buffers ? v be of buffer is constant with amplifier i bias change ? excellent matching between amplifiers ? linearizing diodes ? high output signal-to-noise ratio ? pb?free packages are available* applications ? multiplexers ? timers ? electronic music synthesizers ? dolby ? hx systems ? current-controlled amplifiers, filters ? current-controlled oscillators, impedances *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com pin connections see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 i abca d a +in a ?in a vo a v? in buffera vo buffera i abcb d b +in b ?in b vo b v+ in bufferb vo bufferb n, d packages (top view) pdip?16 n suffix case 648 1 soic?16 d suffix case 751b 1 marking diagrams ne5517yy awlyywwg xx = au or ne yy = an or n a = assembly location wl = wafer lot yy, y = year ww = work week g = pb?free package xx5517dg awlyww 1 1
ne5517, ne5517a, AU5517 http://onsemi.com 2 pin description pin no. symbol description 1 i abca amplifier bias input a 2 d a diode bias a 3 +in a non-inverted input a 4 ?in a inverted input a 5 vo a output a 6 v? negative supply 7 in buffera buffer input a 8 vo buffera buffer output a 9 vo bufferb buffer output b 10 in bufferb buffer input b 11 v+ positive supply 12 vo b output b 13 ?in b inverted input b 14 +in b non-inverted input b 15 d b diode bias b 16 i abcb amplifier bias input b v+ 11 d4 q6 q7 2,15 d2 q4 q5 d3 ?input 4,13 +input 3,14 amp bias input 1,16 q2 q1 d1 v? 6 q10 d6 q11 v output 5,12 q9 q8 d5 q14 q15 q16 r1 d7 d8 q3 7,10 q12 q13 8,9 figure 1. circuit schematic
ne5517, ne5517a, AU5517 http://onsemi.com 3 note: v+ of output buffers and amplifiers are internally connected. b amp bias input b diode bias b input (+) b input (?) b output v+ (1) b buffer input b buffer output amp bias input diode bias input (+) input (?) output v? buffer input buffer output a aa a a a a 123 45 6 7 8 16 15 14 13 12 11 10 9 ? + b + ? a figure 2. connection diagram maximum ratings rating symbol value unit supply voltage (note 1) v s 44 v dc or 22 v power dissipation, t amb = 25 c (still air) (note 2) ne5517n, ne5517an ne5517d, AU5517d p d 1500 1125 mw thermal resistance, junction?to?ambient d package n package r ja 140 94 c/w differential input voltage v in 5.0 v diode bias current i d 2.0 ma amplifier bias current i abc 2.0 ma output short-circuit duration i sc indefinite buffer output current (note 3) i out 20 ma operating temperature range ne5517n, ne5517an AU5517t t amb 0 c to +70 c ?40 c to +125 c c operating junction temperature t j 150 c dc input voltage v dc +v s to ?v s storage temperature range t stg ?65 c to +150 c c lead soldering temperature (10 sec max) t sld 230 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. for selections to a supply voltage above 22 v, contact factory. 2. the following derating factors should be applied above 25 c n package at 10.6 mw/ c d package at 7.1 mw/ c. 3. buffer output current should be limited so as to not exceed package dissipation.
ne5517, ne5517a, AU5517 http://onsemi.com 4 electrical characteristics (note 4) characteristic test conditions symbol AU5517/ne5517 ne5517a unit min typ max min typ max input offset voltage overtemperature range i abc 5.0 a v os 0.4 0.3 5.0 5.0 0.4 0.3 2.0 5.0 2.0 mv v os / t avg. tc of input offset voltage 7.0 7.0 v/ c v os including diodes diode bias current (i d ) = 500 a 0.5 5 0.5 2.0 mv input offset change 5.0 a i abc 500 a v os 0.1 0.1 3.0 mv input offset current i os 0.1 0.6 0.1 0.6 a i os / t avg. tc of input offset current 0.001 0.001 a/ c input bias current overtemperature range i bias 0.4 1.0 5.0 8.0 0.4 1.0 5.0 7.0 a i b / t avg. tc of input current 0.01 0.01 a/ c forward transconductance overtemperature range g m 6700 5400 9600 13000 7700 4000 9600 12000 mho g m tracking 0.3 0.3 db peak output current r l = 0, i abc = 5.0 a r l = 0, i abc = 500 a r l = 0, overtemperature range i out 350 300 5.0 500 650 3.0 350 300 5.0 500 7.0 650 a peak output voltage positive negative r l = , 5.0 a i abc 500 a r l = , 5.0 a i abc 500 a v out +12 ?12 +14.2 ?14.4 +12 ?12 +14.2 ?14.4 v supply current i abc = 500 a, both channels i cc 2.6 4.0 2.6 4.0 ma v os sensitivity positive negative v os / v+ v os / v? 20 20 150 150 20 20 150 150 v/v common-mode rejection ration cmrr 80 110 80 110 db common-mode range 12 13.5 12 13.5 v crosstalk referred to input (note 5) 20 hz < f < 20 khz 100 100 db differential input current i abc = 0, input = 4.0 v i in 0.02 100 0.02 10 na leakage current i abc = 0 (refer to test circuit) 0.2 100 0.2 5.0 na input resistance r in 10 26 10 26 k open-loop bandwidth b w 2.0 2.0 mhz slew rate unity gain compensated sr 50 50 v/ s buffer input current 5 in buffer 0.4 5.0 0.4 5.0 a peak buffer output voltage 5 vo buffer 10 10 v v be of buffer refer to buffer v be test circuit (note 6) 0.5 5.0 0.5 5.0 mv 4. these specifications apply for v s = 15 v, t amb = 25 c, amplifier bias current (i abc ) = 500 a, pins 2 and 15 open unless otherwise specified. the inputs to the buffers are grounded and outputs are open. 5. these specifications apply for v s = 15 v, i abc = 500 a, r out = 5.0 k connected from the buffer output to ?v s and the input of the buffer is connected to the transconductance amplifier output. 6. v s = 15, r out = 5.0 k connected from buffer output to ?v s and 5.0 a i abc 500 a.
ne5517, ne5517a, AU5517 http://onsemi.com 5 typical performance characteristics v out v cmr v out 10 10 10 10 1 peak output current ( a) 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) +125 c 4 3 2 +25 c -55 c 10 10 10 10 10 4 3 2 5 -50 c -25 c0 c25 c50 c75 c100 c125 c 0v (+)v in = (?)v in = v out = 36v leakage current (pa) ambient temperature (t a ) 10 10 10 10 10 transconductance (gm) ? ( ohm) 4 3 2 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) +125 c +25 c -55 c 5 gm mq m m pins 2, 15 open 10 10 1 0.1 0.01 input resistance (meg ) 1 2 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) pins 2, 15 open 10 10 10 10 1 input leakage current (pa) 3 2 4 input differential voltage +125 c +25 c 012345 67 5 input offset voltage (mv) 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) figure 3. input offset voltage v s = 15v +125 c +25 c -55 c +125 c 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 5 peak output voltage and 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) t amb = 25 c v cmr rload = common-mode range (v) 10 10 10 1 0.1 input offset current (na) 2 3 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) figure 4. input bias current v s = 15v +125 c +25 c -55 c 10 10 10 10 1 input bias current (na) 3 4 0.1 a1 a10 a 100 a 1000 a amplifier bias current (i abc ) figure 5. input bias current v s = 15v +125 c +25 c -55 c 2 figure 6. peak output current figure 7. peak output voltage and common-mode range figure 8. leakage current figure 9. input leakage figure 10. transconductance figure 11. input resistance v s = 15v v s = 15v v s = 15v
ne5517, ne5517a, AU5517 http://onsemi.com 6 typical performance characteristics (continued) 1 volt rms (db) 20 0 -20 -40 -60 -80 -100 output voltage relative to 0.1 a1 a10 a 100 a 1000 a i abc amplifier bias current ( a) vs = 15v r l = 10k output noise 20khz bw v in = 40mv p-p v in = 80mv p-p v s = 15v t amb = +25 c c in c out 7 6 5 4 3 2 1 0 0.1 a1 a10 a 100 a 1000 a capacitance (pf) amplifier bias current (i abc ) 0.1 a1 a10 a 100 a 1000 a 2000 1800 1600 1400 1200 1000 800 600 400 200 0 amplifier bias voltage (mv) amplifier bias current (i abc ) -55 c +25 c +125 c output distortion (%) 100 10 1 0.1 0.01 1 10 100 1000 differential input voltage (mv p-p ) 600 500 400 300 200 100 0 10 100 1k 10k 100k output noise current (pa/hz) frequency (hz) i abc = 1ma i abc = 100 a figure 12. amplifier bias voltage vs. amplifier bias current figure 13. input and output capacitance figure 14. distortion vs. differentia l input voltage figure 15. voltage vs. amplifier bias current figure 16. noise vs. frequency i abc = 1ma r l = 10k figure 17. leakage current test circuit figure 18. differential input current test circuit figure 19. buffer v be test circuit 4, 13 2, 15 3, 14 ? + ne5517 11 6 1, 15 5, 12 7, 10 8, 9 a +36v 4, 13 2, 15 3, 14 ? + ne5517 11 6 1, 10 5, 12 a +15v ?15v 4v v v+ 50k v?
ne5517, ne5517a, AU5517 http://onsemi.com 7 applications 4, 13 2, 15 3, 14 ? + ne5517 11 6 5, 12 1, 16 +15v ?15v 7, 10 8, 9 input output 390pf ?15v 51 0.01 f 0.001 f 0.01 f figure 20. unity gain follower 10k 1.3k 10k 62k 5k circuit description the circuit schematic diagram of one-half of the AU5517/ne5517, a dual operational transconductance amplifier with linearizing diodes and impedance buffers, is shown in figure 21. transconductance amplifier the transistor pair, q 4 and q 5 , forms a transconductance stage. the ratio of their collector currents (i 4 and i 5 , respectively) is defined by the differential input voltage, v in , which is shown in equation 1. v in kt q in i 5 i 4 (eq. 1) where v in is the difference of the two input voltages kt ? 26 mv at room temperature (300 k). transistors q 1 , q 2 and diode d 1 form a current mirror which focuses the sum of current i 4 and i 5 to be equal to amplifier bias current i b : i 4 i 5 i b (eq. 2) if v in is small, the ratio of i 5 and i 4 will approach unity and the taylor series of in function can be approximated as kt q in i 5 i 4 kt q i 5 i 4 i 4 (eq. 3) and i 4 i 5 i b kt q in i 5 i 4 kt q i 5 i 4 1 2i b 2kt q i 5 i 4 i b v in (eq. 4) i 5 i 4 v in i b q 2kt the remaining transistors (q 6 to q 11 ) and diodes (d 4 to d 6 ) form three current mirrors that produce an output current equal to i 5 minus i 4 . thus: v in i b q 2kt i o (eq. 5) the term i b q 2kt is then the transconductance of the amplifier and is proportional to i b . v+ 11 d4 q6 q7 2,15 d2 q4 q5 d3 ?input 4,13 +input 3,14 amp bias input 1,16 q2 q1 d1 v? 6 q10 d6 q11 v output 5,12 q9 q8 d5 q14 q15 q16 r1 d7 d8 q3 7,10 q12 q13 8,9 figure 21. circuit diagram of ne5517
ne5517, ne5517a, AU5517 http://onsemi.com 8 linearizing diodes for v in greater than a few millivolts, equation 3 becomes invalid and the transconductance increases non-linearly. figure 22 shows how the internal diodes can linearize the transfer function of the operational amplifier. assume d 2 and d 3 are biased with current sources and the input signal current is i s . since i 4 + i 5 = i b and i 5 ? i 4 = i 0 , that is: i 4 = (i b ? i 0 ), i 5 = (i b + i 0 ) +vs i d i b i 5 q 4 1/2i d i s i s 1/2i d ?vs i 4 i 5 d 3 d 2 i d 2 i s i d 2 i s i 0 i 5 i 4 i 0 2i s i b i d figure 22. linearizing diode for the diodes and the input transistors that have identical geometries and are subject to similar voltages and temperatures, the following equation is true: t q in i d 2 i s i d 2 i s kt q in 1 2(i b i o ) 1 2(i b i o ) (eq. 6) i o i s 2 i b i d for |i s |
i d 2 the only limitation is that the signal current should not exceed i d . impedance buffer the upper limit of transconductance is defined by the maximum value of i b (2.0 ma). the lowest value of i b for which the amplifier will function therefore determines the overall dynamic range. at low values of i b , a buffer with very low input bias current is desired. a darlington amplifier with constant-current source (q 14 , q 15 , q 16 , d 7 , d 8 , and r 1 ) suits the need. applications voltage-controlled amplifier in figure 23, the voltage divider r 2 , r 3 divides the input-voltage into small values (mv range) so the amplifier operates in a linear manner. it is: i out v in r 3 r 2 r 3 g m ; v out i out r l ; a v out v in r 3 r 2 r 3 g m r l (3) g m = 19.2 i abc (g m in mhos for i abc in ma) since g m is directly proportional to i abc , the amplification is controlled by the voltage v c in a simple way. when v c is taken relative to ?v cc the following formula is valid: i abc (v c 1.2v) r 1 the 1.2 v is the voltage across two base-emitter baths in the current mirrors. this circuit is the base for many applications of the AU5517/ne5517. 4 6 3 ? + ne5517 5 11 1 7 8 v in r 4 = r 2 / /r 3 +v cc v c r 2 r 3 r 1 r l r s +v cc int v out ?v cc i out i abc typical values: r 1 = 47k r 2 = 10k r 3 = 200 r 4 = 200 r l = 100k r s = 47k int figure 23.
ne5517, ne5517a, AU5517 http://onsemi.com 9 stereo amplifier with gain control figure 24 shows a stereo amplifier with variable gain via a control input. excellent tracking of typical 0.3 db is easy to achieve. with the potentiometer, r p , the offset can be adjusted. for ac-coupled amplifiers, the potentiometer may be replaced with two 510 resistors. modulators because the transconductance of an ota (operational transconductance amplifier) is directly proportional to i abc , the amplification of a signal can be controlled easily. the output current is the product from transconductance input voltage. the circuit is effective up to approximately 200 khz. modulation of 99% is easy to achieve. 4 3 ? + ne5517/a 11 +v cc 8 v out1 ?v cc 13 6 14 ? + ne5517/a 9 v c r s v out2 ?v cc v in1 v in2 r in r in r p +v cc r d 1 16 12 r l +v cc int int +v cc r l 10 i abc i abc 15 r p +v cc r d 1k r c 1k figure 24. gain-controlled stereo amplifier 10k 30k 10k 15k 15k 10k 10k 5.1k ?v cc 4 6 3 ? + ne5517/a 8 r s v out ?v cc v in1 1 11 +v cc r l 5 i d 2 r c v in2 signal i abc 7 carrier int int +v cc v os figure 25. amplitude modulator 30k 15k 1k 10k 10k
ne5517, ne5517a, AU5517 http://onsemi.com 10 voltage-controlled resistor (vcr) because an ota is capable of producing an output current proportional to the input voltage, a voltage variable resistor can be made. figure 26 shows how this is done. a voltage presented at the r x terminals forces a voltage at the input. this voltage is multiplied by g m and thereby forces a current through the r x terminals: r x r r a g m r a where g m is approximately 19.21 mhos at room temperature. figure 27 shows a v oltage controlled resistor using linearizing diodes. this improves the noise performance of the resistor. voltage-controlled filters figure 28 shows a voltage controlled low-pass filter. the circuit is a unity gain buffer until x c /g m is equal to r/r a . then, the frequency response rolls off at a 6db per octave with the ?3 db point being defined by the given equations. operating in the same manner, a voltage controlled high-pass filter is shown in figure 29. higher order filters can be made using additional amplifiers as shown in figures 30 and 31. voltage-controlled oscillators figure 32 shows a voltage-controlled triangle-square wave generator. with the indicated values a range from 2.0 hz to 200 khz is possible by varying i abc from 1.0 ma to 10 a. the output amplitude is determined by i out r out . please notice the differential input voltage is not allowed to be above 5.0 v. with a slight modification of this circuit you can get the sawtooth pulse generator, as shown in figure 33. application hints to hold the transconductance g m within the linear range, i abc should be chosen not greater than 1.0 ma. the current mirror ratio should be as accurate as possible over the entire current range. a current mirror with only two transistors is not recommended. a suitable current mirror can be built with a pnp transistor array which causes excellent matching and thermal coupling among the transistors. the output current range of the dac normally reaches from 0 to ?2.0 ma. in this application, however, the current range is set through r ref (10 k ) to 0 to ?1.0 ma. i dacmax 2 v ref r ref 2 5v 10k 1ma ?v cc 4 3 ? + ne5517/a 8 v out ?v cc 11 +v cc r x 5 i o 2 r 7 int int c +v cc v c r x r r a g m r a figure 26. vcr 30k 200 200 100k 10k ?v cc 4 3 ne5517/a 8 ?v cc 11 +v cc r x 5 i d 2 r 7 int int c +v cc v c +v cc v os r p 1 6 figure 27. vcr with linearizing diodes 30k 1k 100k 10k
ne5517, ne5517a, AU5517 http://onsemi.com 11 f o r a g m g(r ra) 2 c note: ?v cc 4 3 ? + ne5517/a 8 v out ?v cc 11 +v cc 5 i abc 2 r 7 int int c +v cc v c r a 1 150pf 6 v in figure 28. voltage-controlled low-pass filter 30k 100k 200 200 100k 10k f o r a g m g(r ra) 2 c note: ?v cc 4 3 ? + ne5517/a 8 v out ?v cc 11 +v cc 5 i abc 2 r 7 int int c +v cc v c r a 1 6 v os null +v cc -v cc 0.005 f figure 29. voltage-controlled high-pass filter 30k 100k 1k 1k 100k 10k note: f o r a g m (r r a )2 c +v cc ? + ne5517/a v out ?v cc +v cc int int v c r a 200pf ? + ne5517/a +v cc r a r c ?v cc 100pf -v cc v in r a 200 figure 30. butterworth filter ? 2nd order 100k 200 100k 10k 200 100 k 200 15k 10k c 2
ne5517, ne5517a, AU5517 http://onsemi.com 12 +v cc ? + ne5517/a v out ?v cc +v cc int int v c 800pf ? + ne5517/a +v cc ?v cc 800pf ?v cc 6 11 3 2 1 5 7 13 15 14 12 10 16 low pass 9 bandpass out figure 31. state variable filter 10k 1k 20k 20k 5.1k 1k 15k 20k 5.1k +v cc + ? ne5517/a v out2 ?v cc +v cc int int + ? ne5517/a +v cc ?v cc ?v cc 6 11 4 3 5 7 14 13 12 10 v out1 gain control 1 16 v c c 0.1 f 8 int +v cc 9 figure 32. triangle?square wave generator (vco) 30k 20k 47k 10k i b note: v pk (v c 0.8) r 1 r 1 r 2 t h 2v pk xc i b t l 2v pk xc i c f osc i c 2v pk xc i c
i b +v cc ? + ne5517/a v out2 ?v cc +v cc int int ? + ne5517/a +v cc ?v cc ?v cc 6 11 4 3 5 7 14 13 12 10 v out1 1 16 v c c 0.1 f 8 int +v cc 2 r 1 r 2 i c figure 33. sawtooth pulse vco 470k 30k 20k 30k 47k 30k
ne5517, ne5517a, AU5517 http://onsemi.com 13 ordering information device temperature range package shipping ? AU5517dr2 ?40 to +125 c soic?16 2500 tape & reel AU5517dr2g soic?16 (pb?free) ne5517d 0 to +70 c soic?16 48 units/rail ne5517dg soic?16 (pb?free) ne5517dr2 soic?16 2500 tape & reel ne5517dr2g soic?16 (pb?free) ne5517n pdip?16 25 units/rail ne5517ng pdip?16 (pb?free) ne5517an pdip?16 ne5517ang pdip?16 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ne5517, ne5517a, AU5517 http://onsemi.com 14 package dimensions soic?16 case 751b?05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip?16 case 648?08 issue t on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ne5517/d dolby is a registered trademark of dolby laboratories inc., san francisco, calif. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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